Convolutional neural networks (CNNs) have gained much attention since they can provide superior complex image classification compared to conventional computing systems. To implement CNNs in the memory array, various artificial synapses have been investigated. Among them, ferroelectric transistor is thought to be one of the promising candidates due to its low power consumption, high controllability, and high scalability. However, the development of an efficient operation method for synaptic array and experimental demonstration of its image classification performance have not been reported. Korean researchers at Pohang University of Science and Technology (POSTECH) report the development of artificial neural networks based on ferroelectric thin-film transistor (FeTFT) synaptic arrays which can perform efficient parallel programming and image data processing. The study appears in the journal Science Advances in April 2022. 

The researchers developed FeTFTs as high-performance artificial synapses and integrated into array structure for CNN applications. Until now, sequential programming method where the devices are programmed one by one was suggested as the operation method of FeTFT array, but the researchers developed a novel parallel programming method that can drastically reduce the training time of FeTFT array by programming multiple synapses at once. Using the developed parallel programming method, extraction of image features is performed. Finally, a high classification accuracy over 90% was achieved for the classification of the objects in the images.

Prof. Lee said that "we showed for the first time how to operate the FeTFT synaptic array with parallel programming method, which could drastically decrease the training time of neural networks". "Also, the neural networks based on FeTFT synaptic array could achieve classification accuracy over 90% and all processes and materials are compatible with current semiconductor device fabrication, so we expect that our findings will provide core technology to develop high-performance neural networks in the near future", Prof. Lee said.

[Reference] Kim M.-K. et al., (2022) “CMOS-compatible compute-in-memory accelerators based on integrated ferroelectric synaptic arrays for convolution neural networks.” Science Advances

[Main Author] Min-Kyu Kim (Pohang University of Science and Technology), Ik-Jyae Kim (Pohang University of Science and Technology), Jang-Sik Lee (Pohang University of Science and Technology) 

* Contact : jangsik@postech.ac.kr