Hardware-based neural networks can provide a significant breakthrough in next-generation computing applications due to their ability to extract features from unstructured data and learn from them. However, realizing complex hardware-based neural networks remains challenging because different tasks, such as feature extraction and classification, should be performed at different memory elements and arrays. This further increases the required number of memory arrays and chip size. Prof. Jang-Sik Lee and his team at Pohang University of Science and Technology (POSTECH) reported the development of a highly-scaled and fully-integrated three-dimensional ferroelectric transistor array that can perform efficient layer-by-layer parallel computation. The study appeared in the journal Nature Communications recently. 

The researchers developed ferroelectric transistors as a next-generation memory and integrated them into a three-dimensional array structure. Until now, most of the next-generation memory arrays have been fabricated in two-dimensional structures, but the researchers suggested a layer-by-layer computation method in the three-dimensional array that could drastically increase the computation speed by performing different tasks in each layer. Using the three-dimensional array and layer-by-layer computation method, the classification of complex data, such as color-mixed patterns, was achieved.

Prof. Lee said, "we showed for the first time how to integrate ferroelectric memories in high-density, three-dimensional architecture, which can drastically increase the density of memory array." "Also, the proposed layer-by-layer computation method can lead to faster data processing by parallel computation in three-dimensional architecture, so we expect that our findings will provide a basis to develop high-performance next-generation computing devices and architectures."

Sturcutre of three-dimensional ferroelectric transistor array for next generation computing and its layer-by-layer parallel data processing method. Reproduced under terms of the CC-BY license. Copyright 2023, published by Springer Nature.

[Reference] Kim I. -J. et al., (2023) “Highly-scaled and fully-integrated 3-dimensional ferroelectric transistor array for hardware implementation of neural networks.” Nature Communications

DOI: https://doi.org/10.1038/s41467-023-36270-0

[Main Author] Ik-Jyae Kim (Pohang University of Science and Technology), Jang-Sik Lee (Pohang University of Science and Technology)  

* Contact email : Professor Jang-Sik Lee (jangsik@postech.ac.kr)